(a) Field of the Invention
The present invention relates to a terminal-integrated metal base package module and a terminal-integrated packaging method for a metal base package module. More particularly, the present invention relates to a terminal-integrated metal base package module that enables to easily manufacture a metal base package module that can be easily mounted and has low possibility in short-circuit or damage by utilizing a part of a metal substrate as an external connection terminal for connection with an external circuit, and a terminal-integrated package method for a metal base package module.
(b) Description of the Related Art
A packaging process in a semiconductor element manufacturing process protects a semiconductor chip from an external environment, shaping the semiconductor chip for convenient use, and increase reliability of the semiconductor element by protecting an operation function in the semiconductor chip.
As the degree of integration of semiconductor elements is increased and various functions are provided to the semiconductor elements, the packaging process tends to be changed from a process suitable for a small number of pins of a package to a process suitable for a large number of pins of the package. In addition, a conventional structure for mounting the package on a printed circuit board (PCB) has been replaced with a surface mounting structure. Many types of packages with the surface mounting structure have been proposed, for example a small outline package (SOP), a plastic leaded chip carrier (PLCC), a quad flat package (QFP), a ball grid array (BGA), and a chip scale package (CSP).
A base substrate used in a chip carrier or a printed circuit board (PCB) associated with the semiconductor element needs to have thermal, electrical, and mechanical stability. Conventionally, an expensive ceramic substrate or a resin substrate made of polyimide-based resin, fluoride-based resin, or silicon-based resin has been used as the base substrate for the chip carrier or the PCB. The ceramic substrate or the resin substrate are made of an insulation material so that coating of an insulation material is not required after a through hole process. However, the resin substrates are made of an expensive material and have poor water-resistance and heat-resistance so that it is not usable for a chip carrier substrate. Although the ceramic substrate has better heat resistance than that of the resin substrate, the ceramic substrate has problems in that the ceramic substrate is also expensive and hard to process, and has a high production cost.
In order to overcome such a drawback of the ceramic or resin substrate, use of a metallic substrate has been proposed. The metallic substrate metal material has merits in that it is inexpensive, easily processed, and has good thermal reliability. However, an insulation treatment that is not required in the resin or ceramic substrate should be additionally performed for the metallic substrate, and wire bonding is required to connect a part (e.g., photonic element, semiconductor chip, passive element, VOC, and the like) mounted on the substrate with an external circuit (e.g., driving circuit). Particularly, short-circuit, breakage, or damage may occur during the wire bonding.
The Korean Patent Nos. 10-0656295, 10-0656300, 10-0625196disclosed recently introduced and developed package module techniques using a metal substrate. The disclosed techniques complete a module including a semiconductor chip by forming an oxide layer in an inexpensive metal substrate and provide a package module having an excellent high-frequency characteristic semiconductor process comparability, high thermal reliability, and EMI and EMC stability.
In general, a completed semiconductor chip is completed again through a professional packaging company. A typical packaging process includes die bonding of a semiconductor chip to a lead frame through re-distribution of the semiconductor chip, wire bonding of an external terminal and the semiconductor chip, and protecting the lead frame and the semiconductor chip using an encapsulated molding compound (EMC) for protection of a final semiconductor chip. This is referred to as a back-end process. The back-end process costs 30% of the cost price of the completed semiconductor package, and requires equipment for rearranging the semiconductor chip to the lead frame and wire bonding equipment.
In order to reduce expenses for the back-end process and downsize the semiconductor chip, a wafer level packaging (WLP) technique has been developed and used. According to most of the WLP methods, a ball is formed in an electrode pad and connected with an external circuit using a flip-chip method, or a pad is formed and connected with the external circuit using wire bonding method. However, the flip-chip method is expensive packaging method and has problems of expensive equipment, reliability in the element, and throughput, so that package manufacturers tend to avoid the flip-chip method.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.